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Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families 135
Datasheet Volume One
Thermal Management Specifications
5.1.4.2 8-Core LV70W Thermal Specifications
Notes:
1. These values are specified at V
CC_MAX
for all processor frequencies. Systems must be designed to ensure
the processor is not to be subjected to any static V
CC
and I
CC
combination wherein V
CC
exceeds V
CC_MAX
at
specified ICC. Please refer to the electrical loadline specifications in Section 7.8.1.
2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the
maximum power that the processor can dissipate. TDP is measured at maximum T
CASE
.
3. These specifications are based on initial final silicon simulations, which will be updated as further
characterization data becomes available.
4. Power specifications are defined at all VIDs found in Table 7-3. The processor may be delivered under
multiple VIDs for each frequency.
5. FMB, or Flexible Motherboard, guidelines provide a design target for meeting all planned processor
frequency requirements.
65 66.6 81.6 74 89
70 67.7 82.7 75 90
75 68.7 83.7 77 92
80 69.8 84.8 79 94
85 70.9 85.9 80 95
90 72.0 87.0 82 97
95 73.0 88.0 84 99
Table 5-29. Tcase: 8-Core LV70W Thermal Specifications, Embedded Server SKU
Core
Frequency
Thermal Design
Power (W)
Minimum
T
CASE
(°C)
Maximum
T
CASE
(°C)
Notes
Launch to FMB 70 5 See Figure 5-30 and Table 5-30 1, 2, 3, 4, 5
Table 5-28. 8-Core LV95W Thermal Profiles, Embedded Server SKU (Sheet 2 of 2)
Maximum T
CASE
(ºC)
Maximum DTS (ºC)
Power (W)
Long Term Short Term Long Term Short Term
Figure 5-30. Tcase: 8-Core LV70W Thermal Profile, Embedded Server SKU
- Datasheet - Volume One 1
- Contents 3
- Datasheet Volume One 10
- Revision History 11
- 1 Overview 13
- Overview 14
- 1.2 Interfaces 15
- 1.2.2 PCI Express* 16
- Transaction 18
- 1.3 Power Management Support 19
- 1.5 Package Summary 20
- 1.6 Terminology 20
- 1.7 Related Documents 23
- 1.8 State of Data 24
- 2 Interfaces 25
- 2.2 PCI Express* Interface 26
- 2.2.1.1 Transaction Layer 27
- 2.2.1.2 Data Link Layer 27
- 2.2.1.3 Physical Layer 27
- 2.3.1 DMI2 Error Flow 28
- 2.3.3 DMI2 Link Down 28
- Interfaces 29
- 2.5.2 Client Command Suite 31
- 2.5.2.2 GetDIB() 32
- Reserved 33
- # of Domains 33
- Byte# 5 33
- 2.5.2.3 GetTemp() 34
- 2.5.2.4 RdPkgConfig() 35
- 2.5.2.5 WrPkgConfig() 36
- Channel Temperature Data 43
- 816232431 43
- DRAM Power Limit Performance 45
- CPU ID Data 49
- 2.5.2.7 RdIAMSR() 60
- 2.5.2.8 RdPCIConfig() 64
- 2.5.2.9 RdPCIConfigLocal() 65
- 2.5.2.10 WrPCIConfigLocal() 67
- 2.5.3.1 Power-up Sequencing 69
- 2.5.3.2 Device Discovery 70
- 2.5.3.3 Client Addressing 70
- 2.5.3.4 C-states 71
- 2.5.3.5 S-states 72
- 2.5.3.6 Processor Reset 72
- 2.5.5.1 Abort FCS 75
- 2.5.5.2 Completion Codes 75
- 2.5.7.1 Format 76
- 2.5.7.2 Interpretation 76
- 2.5.7.3 Temperature Filtering 77
- 3 Technologies 79
- 3.1.2 Intel VT-x Features 80
- 3.1.3 Intel VT-d Objectives 80
- 3.2 Security Technologies 81
- (Intel® AES-NI) 82
- 3.2.4 Execute Disable Bit 83
- 4 Power Management 87
- Table 4-6. Intel QPI States 89
- 4.2.2 Low-Power Idle States 90
- 4.2.4.2 Core C1/C1E State 92
- 4.2.4.1 Core C0 State 92
- 4.2.4.3 Core C3 State 93
- 4.2.4.4 Core C6 State 93
- 4.2.4.5 Core C7 State 93
- 4.2.4.6 C-State Auto-Demotion 93
- 4.2.5 Package C-States 94
- 4.2.5.1 Package C0 95
- 4.2.5.2 Package C1/C1E 95
- 4.2.5.3 Package C2 State 96
- 4.2.5.4 Package C3 State 96
- 4.2.5.5 Package C6 State 96
- 4.3.2.1 Self Refresh Entry 98
- 4.3.2.2 Self Refresh Exit 98
- 4.3.2.3 DLL and PLL Shutdown 99
- 5 Thermal Management 101
- Platform 125
- 4600 Product Family 127
- 5.2.1 Processor Temperature 138
- 5.2.2.2 Clock Modulation 140
- 5.2.5 THERMTRIP_N Signal 141
- 6 Signal Descriptions 143
- 6.5 PECI Signal 147
- 6.7 JTAG and TAP Signals 147
- Miscellaneous Signals 148
- 7 Electrical Specifications 153
- 7.1.9.2 Decoupling Guidelines 156
- 7.2 Signal Group Summary 160
- 7.5 Mixing Processors 165
- AP-485, Intel® Processor 166
- 7.8 DC Specifications 168
- Core Supply, Processor 170
- Current on V 170
- Figure 7-3. 8/6-Core: V 172
- • 0-135 A for 95 W processor 173
- 7.8.2.1 V 175
- Overshoot Specifications 175
- Time [us] 176
- Unit Figure Notes 178
- O_ABS_MAX 181
- 7.9 Signal Quality 183
- 7.9.5.3 Activity Factor 185
- Specifications 185
- 8 Processor Land Listing 187
- Processor Land Listing 188
- 8.2 Listing by Land Number 212
- 9 Package Mechanical 237
- 9.7 Processor Materials 242
- 9.8 Processor Markings 242
- 10.1 Introduction 243
- Keepout Zones 245
- PWM Control 254
- Frequency Range 254
- 21,000 25,000 28,000 Hz 254
- 10.4 Boxed Processor Contents 256
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